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1 Dec 2018 ... Power on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 70 ... 72. 5.3.1. Slowing down system clocks . ... SPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 742 ... 31.12 FPB (Flash patch breakpoint) . ... 0. 0. 0. 0. 0. 0x10. GPIOx. _BSRR. BR[15:0]. BSR[15:0]. Reset value. 0. 0. 0. 0.
